Struct riot_sys::NRF_UARTE_Type[][src]

#[repr(C)]
pub struct NRF_UARTE_Type {
Show 43 fields pub TASKS_STARTRX: u32, pub TASKS_STOPRX: u32, pub TASKS_STARTTX: u32, pub TASKS_STOPTX: u32, pub RESERVED: [u32; 7], pub TASKS_FLUSHRX: u32, pub RESERVED1: [u32; 52], pub EVENTS_CTS: u32, pub EVENTS_NCTS: u32, pub EVENTS_RXDRDY: u32, pub RESERVED2: u32, pub EVENTS_ENDRX: u32, pub RESERVED3: [u32; 2], pub EVENTS_TXDRDY: u32, pub EVENTS_ENDTX: u32, pub EVENTS_ERROR: u32, pub RESERVED4: [u32; 7], pub EVENTS_RXTO: u32, pub RESERVED5: u32, pub EVENTS_RXSTARTED: u32, pub EVENTS_TXSTARTED: u32, pub RESERVED6: u32, pub EVENTS_TXSTOPPED: u32, pub RESERVED7: [u32; 41], pub SHORTS: u32, pub RESERVED8: [u32; 63], pub INTEN: u32, pub INTENSET: u32, pub INTENCLR: u32, pub RESERVED9: [u32; 93], pub ERRORSRC: u32, pub RESERVED10: [u32; 31], pub ENABLE: u32, pub RESERVED11: u32, pub PSEL: UARTE_PSEL_Type, pub RESERVED12: [u32; 3], pub BAUDRATE: u32, pub RESERVED13: [u32; 3], pub RXD: UARTE_RXD_Type, pub RESERVED14: u32, pub TXD: UARTE_TXD_Type, pub RESERVED15: [u32; 7], pub CONFIG: u32,
}
Expand description

@brief UART with EasyDMA 0 (UARTE0)

Fields

TASKS_STARTRX: u32

< (@ 0x00000000) Start UART receiver

TASKS_STOPRX: u32

< (@ 0x00000004) Stop UART receiver

TASKS_STARTTX: u32

< (@ 0x00000008) Start UART transmitter

TASKS_STOPTX: u32

< (@ 0x0000000C) Stop UART transmitter

RESERVED: [u32; 7]TASKS_FLUSHRX: u32

< (@ 0x0000002C) Flush RX FIFO into RX buffer

RESERVED1: [u32; 52]EVENTS_CTS: u32

< (@ 0x00000100) CTS is activated (set low). Clear To Send.

EVENTS_NCTS: u32

< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send.

EVENTS_RXDRDY: u32

< (@ 0x00000108) Data received in RXD (but potentially not yet transferred to Data RAM)

RESERVED2: u32EVENTS_ENDRX: u32

< (@ 0x00000110) Receive buffer is filled up

RESERVED3: [u32; 2]EVENTS_TXDRDY: u32

< (@ 0x0000011C) Data sent from TXD

EVENTS_ENDTX: u32

< (@ 0x00000120) Last TX byte transmitted

EVENTS_ERROR: u32

< (@ 0x00000124) Error detected

RESERVED4: [u32; 7]EVENTS_RXTO: u32

< (@ 0x00000144) Receiver timeout

RESERVED5: u32EVENTS_RXSTARTED: u32

< (@ 0x0000014C) UART receiver has started

EVENTS_TXSTARTED: u32

< (@ 0x00000150) UART transmitter has started

RESERVED6: u32EVENTS_TXSTOPPED: u32

< (@ 0x00000158) Transmitter stopped

RESERVED7: [u32; 41]SHORTS: u32

< (@ 0x00000200) Shortcuts between local events and tasks

RESERVED8: [u32; 63]INTEN: u32

< (@ 0x00000300) Enable or disable interrupt

INTENSET: u32

< (@ 0x00000304) Enable interrupt

INTENCLR: u32

< (@ 0x00000308) Disable interrupt

RESERVED9: [u32; 93]ERRORSRC: u32

< (@ 0x00000480) Error source Note : this register is read / write one to clear.

RESERVED10: [u32; 31]ENABLE: u32

< (@ 0x00000500) Enable UART

RESERVED11: u32PSEL: UARTE_PSEL_Type

< (@ 0x00000508) Unspecified

RESERVED12: [u32; 3]BAUDRATE: u32

< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source selected.

RESERVED13: [u32; 3]RXD: UARTE_RXD_Type

< (@ 0x00000534) RXD EasyDMA channel

RESERVED14: u32TXD: UARTE_TXD_Type

< (@ 0x00000544) TXD EasyDMA channel

RESERVED15: [u32; 7]CONFIG: u32

< (@ 0x0000056C) Configuration of parity and hardware flow control

Trait Implementations

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